Friday, January 6, 2012
Thursday, January 5, 2012
LC passive circuit
notch filter
AC sweep
bode plot
bandwidth is very narrow.
looks like low pass filter
except it resonate near (LC)^-0.5
at resonant frequency, output goes unstable.
Wednesday, January 4, 2012
log amplifier, exponential amplifier, precision amplifier
log amplifier with diode
dc sweep log scale linear
Vout = -Vt*ln(Vin/(Is*R)), Is saturation current of diode.
log amplifier with transistor
dc sweep log scale linear
exponential amplifier
linear scale exponential
Vout ~ -R*Is*exp(Vin/Vt).
full wave rectifier
~1.4v drop across diodes
pricision rectifier
rectifier with no voltage drop on diode
Monday, January 2, 2012
bistable, astable, monostable circuit
bistable
dc sweep -10 to 10v, transition happens at (L+)*[R1/(R1+R2)]. (L+ amplifier supply V+, in this case 15v)dc sweep 10 to -10v, transition happens at (L-)*[R1/(R1+R2)]. (L- amplifier supply V-, in this case -15v)
astable
excited with impulse, disturbing the banlance point at 0v, we got a viberator.Viberation period ~ R3*C1 = 0.1s
output is also 0.1s periodic. when output is positive, capacitor is charged, U1- increases till it hits the threshold (L+)*[R1/(R1+R2)]. Then output plummets to negetive, capacitor is discharged, U1- decreases untill it his the threshold (L-)*[R1/(R1+R2)]. Then output bounces to positive, capacitor is charged...
monostable
D5 is used to isolate V3 after the pulse goes through.
excited with positive pulse, U1+ is positive, (Uout - U1+)/R2 = U1+/R1, Uout = [(R2+R1)/R1]*U1+, Uout is also positive. D4 is reversely biased, and is like an open. Capacitor is charged. U1- increases untill it hits (L+)*[R1/(R1+R2)]. Then Uout plummets to negative. Capacitor is discharged. U1- decreases to -0.7v. Diode is foward biased. U1- can decrease no more. Circuit becomes stable.
Even with high energy pulse, after a jerk, Vout settles down.
Sunday, January 1, 2012
cross-over distortion
output stage of an op-amp. when -0.6<v0<0.6v, vout = 0. cross-over distortion because Vbe of Q1 and Q2 are too low to turn the transistors on.
By adding two diodes, we can increase Veb of Q1 and Q2 and force them to turn on.
Increase current at current source will increase voltage across diodes. At I = 0.1mA, we see the distortion is reduced.
At I = 2mA, voltage across diodes are high enough to turn Q1, Q2 fully on. Distortion eliminated.
Alternertively we can replace diodes with transistors, same principle.
When I = 0, distortion.
when I = 10uA, distortion reduced.
When I = 40uA, distortion eliminated.
Input 1mV sin wave.
When I = 0, working within distortion range of input, output is unresponsive. (few uV).
When I = 40uA, get rid of distortion, output is significant. (400mV).
By adding two diodes, we can increase Veb of Q1 and Q2 and force them to turn on.
At I = 2mA, voltage across diodes are high enough to turn Q1, Q2 fully on. Distortion eliminated.
Alternertively we can replace diodes with transistors, same principle.
When I = 0, distortion.
when I = 10uA, distortion reduced.
When I = 40uA, distortion eliminated.
Input 1mV sin wave.
When I = 0, working within distortion range of input, output is unresponsive. (few uV).
When I = 40uA, get rid of distortion, output is significant. (400mV).
Saturday, December 31, 2011
BJT output current protection
There is a current limit near the output.
Increasing current across the resistors above 0.7v will turn Q1, Q4 on. Excess current drained from Q1 and Q4.
circuit resilient to current surge, but not permanent current change. As output should remain at 0 vdc. Ideas base current for Q2 and Q3 is 175mA.
Increasing current across the resistors above 0.7v will turn Q1, Q4 on. Excess current drained from Q1 and Q4.
circuit resilient to current surge, but not permanent current change. As output should remain at 0 vdc. Ideas base current for Q2 and Q3 is 175mA.
Friday, December 30, 2011
BJT active load
DC input at base of Q1, Q2 raise from 0 to 100V, current at wilder current source varies little.
DC voltage at output almost remain constant. (High voltage protection by active load).
Vout = Vc(Q4) = Vc(Q3) ~ V(R10) ~ V(R9 or R11) = I(R9)*R9 ~ (Ic(Q8)/2)*R9.
Current output from wilder current source varies little => Vout varies little.
Ib(Q3) + Ib(Q4) + Ic(Q3) + Ic(Q4) ~ IC(Q8). If Ic increase, Ib will decrease, which in turn result in Ic decrease. The feedback loop of the active load keep system stable.

also the current source becomes unstable.
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