ghdl tb_df2j

ghdl -s df2j.vhd fracmult.vhd lprc1.vhd sregisterbn.vhd tb_df2j.vhd tb_lprc1.vhd
ghdl -i df2j.vhd fracmult.vhd lprc1.vhd sregisterbn.vhd tb_df2j.vhd tb_lprc1.vhd
ghdl -m --warn-error tb_df2j
ghdl -r tb_df2j --stop-time=400ns --vcd=tb_df2j.vcd
C:\ENEL\gtkwave\gtkwave -S script.txt tb_df2j.vcd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_df2j is
end tb_df2j;
architecture Behavioral of tb_df2j is
   component df2j
      Port(
         clk :  in  std_logic;
         enable :  in  std_logic;
         reset :  in  std_logic;
         a1m1 :  in  signed(7 downto 0);
         a2 :  in  signed(7 downto 0);
         fin :  in  signed(15 downto 0);
         fout :  out  signed(15 downto 0)
      );
   end component;
   constant clkPERIOD : time := 10 ns;
   signal W_clk : std_logic;
   signal W_enable : std_logic;
   signal W_reset : std_logic;
   signal W_a1m1 : signed(7 downto 0);
   signal W_a2 : signed(7 downto 0);
   signal W_fin : signed(15 downto 0);
   signal W_fout : signed(15 downto 0);
   signal Trp : std_logic;
begin
   DUT: df2j
      port map(
         clk => W_clk,
         enable => W_enable,
         reset => W_reset,
         a1m1 => W_a1m1,
         a2 => W_a2,
         fin => W_fin,
         fout => W_fout
      );
   defclk: process
      begin
         W_clk <= '0';
         wait for clkPERIOD/2;
         W_clk <= '1';
         wait for clkPERIOD/2;
      end process;
   deftrp: process
     begin
       Trp <= '0';
       wait for 3*clkPERIOD;
       Trp <= '1';
       wait for clkPERIOD;
     end process;
     W_enable <= Trp;
    
   STIMULI: process
      begin
        W_reset <= '0';
         W_a2 <= to_signed(123,8);
         W_a1m1 <= to_signed(111,8);
         W_fin <= to_signed(0,16);
       
        wait for clkPERIOD + 3 ns;
        W_reset <= '1';
        wait for clkPERIOD;        
        W_reset <= '0';
        wait for 4*clkPERIOD;                
        W_fin <= to_signed(1000,16);       
        wait for 2*clkPERIOD;
        W_fin <= to_signed(0,16); 
         assert false report "end of test" severity error;
         wait;
      end process STIMULI;
end Behavioral;
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