multi-stage differential pair

input 100UV sin signal. design so that transistors are in operation mode.

stage1: first differential pair outputs 3mv peak sin signal( 30 times amplification).

stage2: second differential pair outputs 50mv peak deviation sin signal( 16.7 times amplification).

stage3:transistor 5 outputs 900mv peak deviation sin signal( 18 times amplification),
transistor 5 acts as a level shifter as well, design the collector and emitter resistors so that dc voltage at emitter of transistor 5 is 0.7v. (so that output dc voltage at emittor of transistor 6 is 0v).

stage4:900mv peak sin signal output( gain = 1).
transistor 6 acts as a buffer. It has a low output inpedance.

Total gain = 900mv/0.1mv = 9000!